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Philips Semiconductors
Product specification
Octal transceiver/register, non-inverting (3-State)
74ABT652A
FEATURES
* Independent registers for A and B buses * Multiplexed real-time and stored data * 3-State outputs * Live insertion/extraction permitted * Power-up 3-State * Power-up reset * Output capability: +64mA/-32mA * Latch-up protection exceeds 500mA per Jedec JC40.2 Std 17 * ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
DESCRIPTION
The 74ABT652A high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The 74ABT652A transceiver/register consists of bus transceiver circuits with 3-State outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes High. Output Enable (OEAB, OEBA) and Select (SAB, SBA) pins are provided for bus management.
QUICK REFERENCE DATA
SYMBOL tPLH tPHL CIN CI/O ICCZ PARAMETER Propagation delay CPBA to An or CPAB to Bn Input capacitance I/O capacitance Total supply current CONDITIONS Tamb = 25C; GND = 0V CL = 50pF; VCC = 5V VI = 0V or VCC Outputs disabled; VO = 0V or VCC Outputs disabled; VCC =5.5V TYPICAL 3.7 4.3 4 7 110 UNIT ns pF pF A
ORDERING INFORMATION
PACKAGES 24-pin plastic DIP 24-pin plastic SOL 24-pin plastic SSOP Type II 24-pin plastic TSSOP Type I TEMPERATURE RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C ORDER CODE 74ABT652AN 74ABT652AD 74ABT652ADB 74ABT652APW DRAWING NUMBER SOT222-1 SOT137-1 SOT340-1 SOT355-1
PIN CONFIGURATION
CPAB SAB OEAB A0 A1 A2 A3 A4 A5 A6 A7 GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC CPBA SBA OEBA B0 B1 B2 B3 B4 B5 B6 B7
PIN DESCRIPTION
PIN NUMBER 1, 23 2, 22 3, 21 4, 5, 6, 7, 8, 9, 10, 11 20, 19, 18, 17, 16, 15, 14, 13 12 24 SYMBOL CPAB / CPBA SAB / SBA OEAB / OEBA A0 - A7 B0 - B7 GND VCC FUNCTION A to B clock input / B to A clock input A to B select input / B to A select input A to B Output Enable input / B to A Output Enable input (active-Low) Data inputs/outputs (A side) Data inputs/outputs (B side) Ground (0V) Positive supply voltage
SA00094
1995 Apr 19
1
853-1614 15144
Philips Semiconductors
Product specification
Octal transceiver/register, non-inverting (3-State)
74ABT652A
LOGIC SYMBOL
4 5 6 7 8 9 10 11
LOGIC SYMBOL (IEEE/IEC)
21 3
EN1 [BA] EN2 [AB] C4 G5 C6 G7
A0
A1
A2
A3
A4
A5
A6
A7
23 22 1 2
23 22 2 1
CPBA SBA SAB CPAB OEAB OEBA 3 21
4
w1 1 6D 7 7
5 51
4D
20
B0
B1
B2
B3
B4
B5
B6
B7 1
w1 2
20
19
18
17
16
15
14
13
5 6
19 18 17 16 15 14 13
SA00095
7 8 9 10 11
SA00096
FUNCTION TABLE
INPUTS OEAB L L X H L L L L H H H H L X * ** = = = = OEBA H H H H X L L L H H L CPAB H or L H or L X X X H or L H or L CPBA H or L H or L X H or L X X H or L SAB X X X ** X X X X L H H SBA X X X X X ** L H X X H An Input Input Unspecified output* Output Input Output DATA I/O Bn Input Unspecified output* Input Input Output Output OPERATING MODE Isolation Store A and B data Store A, Hold B Store A in both registers Hold A, Store B Store B in both registers Real time B data to A bus Stored B data to A bus Real time A data to B bus Store A data to B bus Stored A data to B bus Stored B data to A bus
High voltage level Low voltage level Don't care Low-to-High clock transition The data output function may be enabled or disabled by various signals at the OEBA and OEAB inputs. Data input functions are always enabled, i.e., data at the bus pins will be stored on every Low-to-High transition of the clock. If both Select controls (SAB and SBA) are Low, then clocks can occur simultaneously. If either Select control is High, the clocks must be staggered in order to load both registers.
1995 Apr 19
2
Philips Semiconductors
Product specification
Octal transceiver/register, non-inverting (3-State)
74ABT652A
The following examples demonstrate the four fundamental bus-management functions that can be performed with the 74ABT652A.
The select pins determine whether data is stored or transferred through the device in real time. The output enable pins determine the direction of the data flow.
REAL TIME BUS TRANSFER BUS B TO BUS A
REAL TIME BUS TRANSFER BUS A TO BUS B
STORAGE FROM A, B, OR A AND B
TRANSFER STORED DATA TO A OR B
A
B
A
B
A
B
A
B
OEABOEBA CPAB CPBA SAB SBA L L X X X L
}
H H
OEABOEBA CPAB CPBA SAB SBA X X L X
}
X L L H X H
OEABOEBA CPAB CPBA SAB SBA X X X X X X X X
}
H L
OEABOEBA CPAB CPBA SAB SBA H|L H|L H H
}
SA00097
1995 Apr 19
3
Philips Semiconductors
Product specification
Octal transceiver/register, non-inverting (3-State)
74ABT652A
LOGIC DIAGRAM
21 OEBA 3 OEAB 23 CPBA 22 SBA 1 CPAB 2 SAB
1of 8 Channels
1D C1 Q
A0
4 1D C1 Q
20
B0
A1 A2 A3 A4 A5 A6 A7
5 6 7 8 9 10 11 DETAIL A X 7
19 18 17 16 15 14 13
B1 B2 B3 B4 B5 B6 B7
SA00098
ABSOLUTE MAXIMUM RATINGS1, 2
SYMBOL VCC IIK VI IOK VOUT IOUT Tstg PARAMETER DC supply voltage DC input diode current DC input voltage3 DC output diode current DC output voltage3 DC output current Storage temperature range VO < 0 output in Off or High state output in Low state VI < 0 CONDITIONS RATING -0.5 to +7.0 -18 -1.2 to +7.0 -50 -0.5 to +5.5 128 -65 to 150 UNIT V mA V mA V mA C
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1995 Apr 19
4
Philips Semiconductors
Product specification
Octal transceiver/register, non-inverting (3-State)
74ABT652A
RECOMMENDED OPERATING CONDITIONS
LIMITS SYMBOL VCC VI VIH VIL IOH IOL t/v Tamb DC supply voltage Input voltage High-level input voltage Low-level input voltage High-level output current Low-level output current Input transition rise or fall rate Operating free-air temperature range 0 -40 PARAMETER Min 4.5 0 2.0 0.8 -32 64 10 +85 Max 5.5 VCC V V V V mA mA ns/V C UNIT
DC ELECTRICAL CHARACTERISTICS
LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb = +25C Min VIK Input clamp voltage VCC = 4.5V; IIK = -18mA VCC = 4.5V; IOH = -3mA; VI = VIL or VIH VOH High-level output voltage VCC = 5.0V; IOH = -3mA; VI = VIL or VIH VCC = 4.5V; IOH = -32mA; VI = VIL or VIH VOL VRST3 II Low-level output voltage Power-up output low voltage Input leakage current IOFF IPU/IPD IIH + IOZH IIL + IOZL ICEX IO ICCH ICCL ICCZ ICC Additional supply current per input pin2 Quiescent supply current Control pins Data pins VCC = 4.5V; IOL = 64mA; VI = VIL or VIH VCC = 5.5V; IO = 1mA; VI = GND or VCC VCC = 5.5V; VI = GND or 5.5V VCC = 5.5V; VI = GND or 5.5V VCC = 0.0V; VO or VI 4.5V VCC = 2.1V; VO = 0.5V; VI = GND or VCC ; VOE = Don't care; VOE = Don't care VCC = 5.5V; VO = 2.7V; VI = VIL or VIH VCC = 5.5V; VO = 0.5V; VI = VIL or VIH VCC = 5.5V; VO = 5.5V; VI = GND or VCC VCC = 5.5V; VO = 2.5V VCC = 5.5V; Outputs High, VI = GND or VCC VCC = 5.5V; Outputs Low, VI = GND or VCC VCC = 5.5V; Outputs 3-State; VI = GND or VCC VCC = 5.5V; one input at 3.4V, other inputs at VCC or GND; VCC = 5.5V -40 2.5 3.0 2.0 Typ -0.9 3.0 3.5 2.4 0.3 0.13 0.01 5 5.0 5.0 5.0 -5.0 5.0 -65 110 20 110 0.3 0.55 0.55 1.0 100 100 50 50 -50 50 -180 250 30 250 1.5 -40 Max -1.2 2.5 3.0 2.0 0.55 0.55 1.0 100 100 50 50 -50 50 -180 250 30 250 1.5 Tamb = -40C to +85C Min Max -1.2 V V V V V V A A A A A A A mA A mA A mA UNIT
Power-off leakage current Power-up/down 3-State output current4 3-State output High current 3-State output Low current Output High leakage current Output current1, 5
NOTES: 1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. This is the increase in supply current for each input at 3.4V. 3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. 4. This parameter is valid for any VCC between 0V and 2.1V, with a transition time of up to 10msec. From VCC = 2.1V to VCC = 5V 10%, a transition time of up to 100sec is permitted. 5. This data sheet limit may vary among suppliers.
1995 Apr 19
5
Philips Semiconductors
Product specification
Octal transceiver/register, non-inverting (3-State)
74ABT652A
AC CHARACTERISTICS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500 LIMITS SYMBOL PARAMETER WAVEFORM Min fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL Maximum clock frequency Propagation delay CPAB to Bn or CPBA to An Propagation delay An to Bn or Bn to An Propagation delay SAB to Bn or SBA to An Output enable time OEBA to An Output disable time OEBA to An Output enable time OEAB to Bn 1 1 2 3 5 6 5 6 5 6 5 6 125 2.2 1.7 1.5 1.5 1.5 1.5 2 3 1.5 1.5 2 3 1.5 1.5 Tamb = +25oC VCC = +5.0V Typ 300 3.7 4.3 3.0 3.6 3.5 4.2 3.2 4.5 3.9 2.9 3.5 4.7 3.8 3.0 5.1 5.1 4.3 4.6 5.1 5.21 4.6 6.8 4.71 3.8 6.1 6.5 4.61 4.4 Max Tamb = -40 to +85oC VCC = +5.0V 0.5V Min 125 2.2 1.7 1.5 1.5 1.5 1.5 2 3 1.5 1.5 2 3 1.5 1.5 5.6 5.6 4.8 5.4 6.5 5.9 5.8 8.5 5.31 4.1 6.5 7.4 5.5 5.1 Max MHz ns ns ns ns ns ns ns UNIT
tPHZ Output disable time OEAB to Bn tPLZ 1. This data sheet limit may vary among suppliers.
AC SETUP REQUIREMENTS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500 LIMITS SYMBOL PARAMETER WAVEFORM Tamb = VCC = +5.0V Min ts(H) ts(L) th(H) th(L) tw(H) tw(L) Setup time An to CPAB, Bn to CPBA Hold time An to CPAB, Bn to CPBA Pulse width, High or Low CPAB or CPBA 4 4 1 3.0 3.0 0.0 0.0 4.0 4.0 +25oC Typ 0.7 0.7 -0.5 -0.5 1.0 1.0 Tamb = -40 to +85oC VCC = +5.0V 0.5V Min 3.0 3.0 0.0 0.0 4.0 4.0 Max ns ns ns UNIT
1995 Apr 19
6
Philips Semiconductors
Product specification
Octal transceiver/register, non-inverting (3-State)
74ABT652A
VM = 1.5V, VIN = GND to 3.0V
1/fMAX An or Bn CPBA or CPAB VM tw(H) tPHL An or Bn VM VM tw(L) tPLH VM VM
VM
VM
ts(H)
CPBA or CPAB
VM
NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance.
SA00087
Waveform 1. Propagation Delay, Clock Input to Output, Clock Pulse Width, and Maximum Clock Frequency
Waveform 4. Data Setup and Hold Times
OEBA An or Bn VM VM tPLH Bn or An VM VM tPHL An or Bn VM VM VOH -0.3V 0V OEAB tPZH tPHZ VM
SA00099
Waveform 2. Propagation Delay, An to Bn or Bn to An
Waveform 5. 3-State Output Enable Time to High Level and Output Disable Time from High Level
OEBA SBA or SAB VM tPHL An or Bn VM VM OEAB tPLH VM tPZL tPLZ VM VM
An or Bn
SA00102
Waveform 3. Propagation Delay, SBA to An or SAB to Bn
Waveform 6. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level
1995 Apr 19
7
EEEEEEEEE E EEEEEEEEE E EEEEEEEEE E EEEEEEEEE E EEEEEEEEE E
VM VM th(H) ts(L) th(L) tW(L) VM
EEE EEE EEE EEE EEE
AC WAVEFORMS
SA00090
SA00100
VM
VOL +0.3V 0V
SA00101
Philips Semiconductors
Product specification
Octal transceiver/register, non-inverting (3-State)
74ABT652A
TEST CIRCUIT AND WAVEFORM
VCC 7.0V RL 90% NEGATIVE PULSE VM 10% tTHL (tF) CL RL POSITIVE PULSE 10% tW tTLH (tR) 90% 90% VM 10% 0V 10% 0V tTLH (tR) tTHL (tF) AMP (V) tW VM 90% AMP (V)
PULSE GENERATOR
VIN D.U.T. RT
VOUT
Test Circuit for 3-State Outputs
VM
SWITCH POSITION
TEST tPLZ tPZL All other SWITCH closed closed open
VM = 1.5V Input Pulse Definition
DEFINITIONS
RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators.
INPUT PULSE REQUIREMENTS FAMILY Amplitude 74ABT 3.0V Rep. Rate 1MHz tW 500ns tR 2.5ns tF 2.5ns
SA00012
1995 Apr 19
8
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